EJT

EJT is a testing system for boards with a JTAG port that allows for the testing of an electronic component or chain of components, and to programme them using Boundary Scanning.

Description

JTAG identifies the Boundary Scan Test (BST) defined by IEEE 1149.1. for integrated circuits. This standard defines the input and output pins, the logical control functions and commands that facilitate plate testing without using specialized equipment.
Boundary-scan architecture is an excellent alternative to in-circuit testing to test electrical connections.

EJT is Eldig’s system for boards with a JTAG port.
The JTAG ports include four or five pins described in the JTAG specifications: TCK, TMS, TDI and TDO. The fifth signal defined in the JTAG specifications is TRST (Test Reset). TRST is considered an optional signal because it is not currently required for BST.
EJT is a testing system to test an electronic component or chain of components, and to programme them using Boundary Scanning. Boundary scanning makes it possible to carry out testing without ad hoc test points or fixtures. This technology can also be used for small-scale testing, which would normally require complex systems. Our product, can be applied to small plates, at low cost.