A fixture comprises two main parts: a base (the underfixture) and a specialist part (the actual fixture or jig). Eldig has recently launched its new line of own-brand fixtures that embody all the advances in technology made in its 30 years of experience.

Description

A fixture comprises two main parts: a base (the underfixture) and a specialist part (the actual fixture or jig).
A fixture (specialized part) is a device, which is mainly interchangeable, to connect electronic equipment using connectors and spring contacts, to a testing machine.

An underfixture, or more simply the base, houses the fixture and connects to and interfaces with the test machine; it is a load-bearing structure with a manually or pneumatically operated pressure mechanism, used to keep the electronic device to be tested pressed down on the fixture.

The fixture is the part which interfaces the system (tester) and the plate to test.
A fixture must be made, usually in trolitax, for each type of plate, which also houses the connectors used for connection to the system.
The fixture consists of a bed of spring tracer points and allows for a quick and reliable connection between the system’s stimulation and measurement instruments and the measurement points of the plate.
The stimulation and measurement points on the plate are connected to the system by spring tracer points; these points comprise the bed of nails (BEOF).
The plate to test is secured by two or more pins, which must maintain a clearance of 3/10 mm.
The underfixture instead consists of a robust metal structure and a (manual or pneumatic) mechanical mechanism to move the upper frame which, as it lowers, connects the BUT (Board Under Test) with the tracer points.
The plate comes into contact with the bed of nails due to the mechanical or pneumatic action of the underfixture, which keeps the plate pressed down on the fixture.

Over the years, Eldig testing has perfected the fixtures it supplies to its customers, based on thirty years’ of experience, continually evaluating possible improvements to its equipment.
A new line of Eldig brand fixtures has recently been launched, embodying all possible improvements in materials, functionality, usability, etc.  

Datasheet

The following are necessary to develop a fixture:
node network description files (net list)
a parts list 
Gerber files 
wiring diagrams
parts assembly diagram 
a bare printed circuit 
at least one functioning assembled plate.

In more detail, the net list must preferably be in a CADNETIX format. For example:

PARTS LIST
                 CONN10         J1
                 CONN12         J5
                 3.15a          FUS1
                 2K2            R1
                 100K           R4
                 100UF          C23
                 1N4148         D1
                 1N4004         D5
                 HEF4021        IC1
                 LM393          IC3
                 74HC244        IC4
EOS
NET LIST
NODENAME AVANM1 $
CDY 8 I3 6 P158 1 RA 4
NODENAME BL5M $
R79 2 R81 1 R22 1 R20 2 P43 1 $
IC3 7 I3 22 C25 2
NODENAME CL1M1 $
P88 1 TP5 1 I4 5 I3 34
NODENAME ENPR_ $
IC4 1 P67 1 D1 2 R6 2 IC4 19 $
R28 2
EOS

Note: The CADNETIX format does not contain information relative to the XY values of the component pins. Parameters therefore have to be taken from other files in which the XY values are associated to the pins: 
A file with XY information referred to the node is shown below:

Part Pin Data Listing:
U12       ATTL7581 DIP16 Pin Net Name X - 5.000 Y - 4.941 Layer
     1     GND     67,31     43,40     0
     2             67,31     40,86     0
     3     TSLICL1 67,31     38,33     0
     4     N00059  67,31     35,78     0
C250      SMT004 Pin Net Name X - 5.000 Y - 4.941 Layer
     1     %PS1    143,63    138,27    1
     2     GND     145,67    138,27    1
TP1       TEST Pin Net Name X - 5.000 Y - 4.941 Layer
     1     -24V     88,90     91,67    2
TP2       TEST Pin Net Name X - 5.000 Y - 4.941 Layer
     1     -48V    127,50     18,64    2

Example of a file generated by FABMASTER "pins.asc":

Part        T/B
Pin   Name      X         Y     Layer  Net               Nail(s)
Part U1     (T)
   1    1    48.920   109.220     1    0VDC
   2   2    48.920   107.950    1 FABMASTER_UNCONNECTED_U1_2
   3    3    48.920   106.680     1    MISOO
   4    4    48.920   105.410     1    OUT92
   5    5    48.920   104.140     1    OUT91
   6    6    48.920   102.870     1    OUT90
   7    7    48.920   101.600     1    OUT89
   8    8    48.920   100.330     1    NMOSI
   9    9    48.920    99.060     1    SCK

Other types of CAD already contain necessary information in a single file such as CADASCII.
Example:

NL|J1|1|CONN2VIE_MSPOX|MRESET|60S40|4725|3600|BOTH|Y
NL|J1|2|CONN2VIE_MSPOX|GND|60R40|4725|3500|BOTH|Y
NL|C46|1|CAP15PF|HITEMD|58X60|3008|125|TOP|N
NL|C46|2|CAP15PF|GND|58X60|3092|125|TOP|N
NL|D1|1|BAR43-|FAN24|30X48|3481|3538|TOP|N
NL|D1|2|BAR43-|Z|30X48|3481|3462|TOP|N
NL|D1|3|BAR43-|FANF24|30X48|3569|3500|TOP|N
NL|VIA|1|VIA|ALINST1|38R20|2751|1885|BOTH|Y
NL|VIA|2|VIA|ALINST2|38R20|3075|2143|BOTH|Y
NL|VIA|4|VIA|CPRES1|38R20|2317|793|BOTH|Y

N.B. The CADASCII-format netlist also contains information relative to the XY values of pins associated to the coordinate and the node-name and accessibility or otherwise of the points. In the previous example, the first row contains the following information:
J1 (2-way connector) pin 1 is connected to the MRESET node at point X=4725, Y=3600 which is a through hole and is accessible.

The NEUTRAL file is another type of file containing all necessary information.
Example:

# file : /user/tracer3/pcb/mfg/neutral_file
# date : Wednesday July 26, 2000; 15:12:31
#
#############################################
###Panel Added Part Information
#############################################
P_ADDP  PANEL  G'  0.0 0.0   1   1   1
P_ADDP  PANEL  LOGO  'LOGO'  0.325 4.395   1   1   1
#############################################
###Nets Information
#############################################
NET /5V
N_PIN RS25-1 1.8965 2.025 ps58x63   2
N_PIN RS6-1 2.1965 2.025 ps58x63   2
N_PIN RS44-2 2.56 0.3 ps35x63   1
N_PIN RS51-2 2.3035 2.15 ps58x63   2
NET /AC_FAIL-00
N_PIN RS17-2 2.9035 0.975 ps58x63   2
N_PIN CR3-3 1.725 0.695 ps40x40   1
#############################################
###Component Information
#############################################
COMP C1 90092104-001 c100nfsfneb a_geom_0805rs_nr  2.525 0.8 1   0
C_PROP (VALUE,"100N") (REFLOC,"IN,-0.055,0.025,0,TL,0.05,SILKSCREEN")
C_PIN C1-1 2.49 0.8  1  1  0 ps35x63 /N$1770
C_PIN C1-2 2.56 0.8  1  1  0 ps35x63 ZGND
COMP Z2 Z0100001-010 con10ra_molex a_geom_10ra_molex  2.704 1.841 1  90
C_PROP(REFLOC,"IN,0.184,0.269,215,0.15,0.01,std,1,PWA_LAYER")
C_PIN Z2-1 2.704 1.841  0  1 90 P71 /VIN_MCC
C_PIN Z2-2 2.704 1.676  0  1 90 P71 ZGND
C_PIN Z2-3 2.704 1.511  0  1 90 P71 /SPARE
C_PIN Z2-4 2.704 1.346  0  1 90 P71 /BAT_LOW-00
C_PIN Z2-5 2.704 1.181  0  1 90 P71 /BAT_FULL-00
C_PIN Z2-6 2.487 1.841  0  1 90 P71 /VIN_MCC
C_PIN Z2-7 2.487 1.676  0  1 90 P71 ZGND
#############################################
###TESTPOINTS
#############################################
T_TEST VIA  /N$1119 1.55 1.588 BOT ptest INSERTED  None
T_TEST VIA  /N$215 1.975 0.2 BOT ptest INSERTED  None
T_TEST VIA  /N$3565 1.807 0.814 BOT vias_th MAPPED  None
T_TEST VIA  /AC_FAIL-00 2.88 1.095 BOT vias_th MAPPED  None
T_TEST VIA  /BAT_OFF+00 1.725 1.574 BOT vias_th MAPPED  None
T_TEST VIA  /DRVSOURCE 1.83 0.615 BOT vias_th MAPPED  None
T_TEST VIA  /N$1039 2.21 0.45 BOT vias_th MAPPED  None
T_TEST VIA  /N$1117 1.829 0.909 BOT vias_th MAPPED  None
T_TEST VIA  /N$1139 2.425 0.745 BOT vias_th MAPPED  None
T_TEST VIA  /N$1164 2.44 0.26 BOT vias_th MAPPED  None

If these formats are not available, other formats with similar characteristics are acceptable.
As regards Gerber files, the WELDING SIDE, COMPONENTS SIDE, DRILL and any TEST POINTS are essential.
An opening descriptor, preferably in a GAP format, is necessary to correctly display the Gerber files. INTERNAL LAYERS plus LC and LS SILK-SCREEN PRINTING and SOLDER are useful.

To sum up:
Parts list 
Wiring diagrams
Ls and Lc parts assembly diagram 
Net list
File with XY values associated to component pins and TP
Gerber files 
Printed circuit 
Assembled plate

Mechanical considerations

1. 2 test points on traverses affected by low impedances (R < 100 Ohm) are necessary.
2. At least two holes on the printed circuit, for the reference pins, are necessary.
These holes:
a) must not be metallized
b) must have a maximum precision diameter
c) must be positioned at the ends of the longest diagonal board
3. The minimum distance between test points must be 82 mls. This distance means that tracer points which are more rigid and reliable over time can be used. In particular cases, a distance of 68mls allows for less robust tracer points to be used.
In exceptional cases, a distance of 50mls allows for very delicate tracer points to be used.
4. The optimal diameter of the Test Point must be greater than 40mls.
The minimum diameter permitted is 32mls.
 
Electrical considerations

1. Avoid blocking signals that are strategic for testing, such as: OE, CS, DIR (typically signals that make it possible to disable, initialise or configure the operating mode of a component plus signals dedicated to testing, e.g. TDI TDO TMS TCK TEST etc.). These signals may be restricted to GND or VCC with resistances of at least 33 Ohm.
2. Integrated oscillators may be isolated with a jumper or with oscillators that may be disabled (OE on pin 1).
3. Buffer batteries or SUPERCAP may be isolated with a jumper, or these components may be assembled after testing.
4. A Test Point should also be provided for signals that are not used, to allow for short circuit testing between all points. Providing all points on the LSIs makes it possible to apply test vectors included in the library, without having to re-write new test patterns which entail additional costs.
5. When possible and with plates that widely use PAL/GAL, provide for tristatable outputs that are controlled by a pin that functions as an OE.
6. Avoid a high resistance parallel with high capacities in order to limit the resistive component ( 7*R*C ) test time.

If the test time 7*R*C > 500mS, split the resistance into a series of two resistances.